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| Freescale Semiconductor, Inc. DSP56824/D Rev. 2.0, 01/2000 Semiconductor Products Sector DSP56824 Freescale Semiconductor, Inc... Technical Data DSP56824 16-Bit Digital Signal Processor The DSP56824 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). This general purpose DSP combines processing power with configuration flexibility, making it an excellent cost-effective solution for signal processing and control functions. Because of its low cost, configuration flexibility, and compact program code, the DSP56824 is well-suited for cost-sensitive applications, such as digital wireless messaging, digital answering machines/feature phones, modems, and digital cameras. The DSP56800 core consists of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MPU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers. The DSP56824 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The rich set of programmable peripherals and ports provides support for interfacing multiple external devices, such as codecs, microprocessors, or other DSPs. The DSP56824 also provides two external dedicated interrupt lines and sixteen to thirty-two General Purpose Input/Output (GPIO) lines, depending on peripheral configuration (see Figure 1). (c) Motorola, Inc., 2000. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 Data Sheet Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP56824 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . For the Latest Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 7 7 Part 2 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clock and Phase Lock Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address, Data, and Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interrupt and Mode Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Peripheral Interface (SPI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timer Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 JTAG/OnCETM Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Freescale Semiconductor, Inc... Part 3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Components for the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A External Bus Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A External Bus Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B and C Pin GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Interface (SSI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 21 22 24 26 29 30 34 36 41 47 48 Part 4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.1 4.2 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Ordering Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Part 5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1 5.2 Thermal Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Electrical Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Part 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Part 1 Overview 16 to 32 GPIO lines 4 8 8 4 4 6 2 Data Memory 3584 x 16 RAM Data Memory 2048 x 16 ROM Serial Synch. Serial Program Timer/ ProgramPeriph. Periph. Serial Memory COP/ Event mable PLL Interrupt GPIO Interface Interface Interface Counters RTI 32 K x 16 ROM (SPI0) (SSI) or or GPIO (SPI1) 128 x 16 RAM GPIO or GPIO or GPIO GPIO PAB Freescale Semiconductor, Inc... Clock Gen. 16-bit DSP56800 Core Address Generation Unit XAB1 XAB2 External Address Bus Switch XDB2 External Data Bus Switch Address 16 PGDB Bit Manipulation Unit PDB CGDB Data 16 Control JTAG/ OnCETM Port Program Controller Data ALU 16 x 16 + 36 36-bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bus Control 4 5 MODA/IRQA MODB/IRQB RESET AA1445 Figure 1. DSP56824 Block Diagram DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. 1.1 Data Sheet Conventions This document uses the following conventions: * * * * * * * * OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. To set a bit or bits means to establish logic level one. To clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. -- Active low signals change from logic level one to logic level zero. -- Active high signals change from logic level zero to logic level one. * Deasserted means that an asserted discrete signal changes logic state. -- Active low signals change from logic level zero to logic level one. -- Active high signals change from logic level on to logic level zero. * LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Freescale Semiconductor, Inc... Please refer to the examples in Table 1. Table 1. Data Conventions Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL 4 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56824 Features 1.2 DSP56824 Features 1.2.1 * * * * * * * Digital Signal Processing Core Efficient 16-bit DSP56800 family DSP engine As many as 35 Million Instructions Per Second (MIPS) at 70 MHz Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C Compiler and local variable support Software subroutine and interrupt stack with unlimited depth Freescale Semiconductor, Inc... * * * * * * 1.2.2 * * Memory On-chip Harvard architecture permits as many as three simultaneous accesses to program and data memory On-chip memory -- 32 K x 16 Program ROM -- 128 x 16 Program RAM -- 3.5 K x 16 X RAM usable for both data and programs -- 2 K x 16 X data ROM * Off-chip memory expansion capabilities -- As much as 64 K x 16 X data memory -- As much as 64 K x 16 program memory -- External memory expansion port programmable for 1 to 15 wait states * Programs can run out of X data RAM 1.2.3 * * * Peripheral Circuits External Memory Interface (Port A) Sixteen dedicated GPIO pins (eight pins programmable as interrupts) Serial Peripheral Interface (SPI) support: Two configurable four-pin ports (SPI0 and SPI1) (or eight additional GPIO lines) -- Supports LCD drivers, A/D subsystems, and MCU systems -- Supports inter-processor communications in a multiple master system -- Supports demand-driven master or slave devices with high data rates DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. * Synchronous Serial Interface (SSI) support: One 6-pin port (or six additional GPIO lines) -- Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola SPI-compliant peripherals -- Allows implementing synchronous or synchronous transmit and receive sections with separate or shared internal/external clocks and frame syncs -- Supports Network mode using frame sync and as many as 32 time slots -- Can be configured for 8-bit, 10-bit, 12-bit, and 16-bit data word lengths * * * Three programmable 16-bit timers (accessed using two I/O pins that can also be programmed as two additional GPIO lines) Computer-Operating Properly (COP) and Real-Time Interrupt (RTI) timers Two external interrupt/mode control pins One external reset pin for hardware reset JTAG/On-Chip Emulation (OnCETM) 5-pin port for unobtrusive, processor speed-independent debugging Extended debug capability with second breakpoint and 8-level OnCE FIFO history buffer Software-programmable, Phase Lock Loop-based (PLL-based) frequency synthesizer for the DSP core clock Freescale Semiconductor, Inc... * * * * 1.2.4 * * * * Energy Efficient Design A single 2.7-3.6 V power supply Power-saving Wait and multiple Stop modes available Fully static, HCMOS design for 70 MHz to dc operating frequencies Available in plastic 100-pin Thin Quad Flat Pack (TQFP) surface-mount package 6 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Product Documentation 1.3 Product Documentation The three documents listed in Table 2 are required for a complete description of the DSP56824 and are necessary to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2. DSP56824 Chip Documentation Topic DSP56800 Family Manual Description Detailed description of the DSP56800 family architecture, and 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56824 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Order Number DSP56800FM/D Freescale Semiconductor, Inc... DSP56824 User's Manual DSP56824 Technical Data Sheet DSP56824UM/D DSP56824/D 1.4 For the Latest Information Refer to the back cover of this document for: * * * * Motorola contact addresses Motorola MfaxTM service Motorola DSP Internet address Motorola DSP Helpline The Mfax service and the DSP Internet connection maintain the most current specifications, documents, and drawings. These two services are available on demand 24 hours a day. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the DSP56824 are organized into functional groups, as shown in Table 3 and as illustrated in Figure 2. In Table 4 through Table 16, each table row describes the signal or signals present on a pin. Figure 2 provides a diagram of DSP56824 signals by functional group. Table 3. Functional Group Pin Allocations Functional Group Number of Pins 10 10 4 16 16 4 3 8 8 8 6 2 5 Detailed Description Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Freescale Semiconductor, Inc... Power (VDD or VDDPLL) Ground (VSS or VSSPLL) PLL and Clock Address Bus Data Bus Bus Control Interrupt and Mode Control Programmable Interrupt General Purpose Input/Output Dedicated General Purpose Input/Output Serial Peripheral Interface (SPI) Ports1 Synchronous Serial Interface (SSI) Port1 Timer Module1 JTAG/On-Chip Emulation (OnCE) 1. Alternately, GPIO pins 8 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Power and Ground Signals DSP56824 Port B Programmable Interrupts/GPIO Dedicated GPIO Port B GPIO VDD VDDPLL VSS VSSPLL 9 9 8 8 XCOLF Power Port Ground PB0-PB7 PB8-PB14 PB15 Port C GPIO EXTAL XTAL CLKO SXFC Port C PLL and Clock SPI0 Port/ GPIO MISO0 MOSI0 SCK0 SS0 MISO1 MOSI1 SCK1 SS1 STD SRD STCK STFS SRCK SRFS TIO01 TIO2 TCK TMS TDI TDO TRST/DE PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 Freescale Semiconductor, Inc... Port A A0-A15 16 External Address Bus External Data Bus External Bus Control SPI1 Port/ GPIO D0-D15 16 SSI Port/ GPIO PS DS RD WR During Reset After Reset Timer Module/ GPIO JTAG/ OnCE Port IRQA IRQB RESET MODA MODB RESET Interrupt/ Mode Control AA1446 Figure 2. DSP56824 Signals Identified by Functional Group 2.2 Power and Ground Signals Table 4. Power Inputs Signal Name (number of pins) VDD (9) Signal Description Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. PLL Power--This pin supplies a quiet power source to the VCO to provide greater frequency stability. VDDPLL DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. Table 5. Grounds Signal Name (number of pins) VSS (9) Signal Description GND--These pins provide grounding for the internal structures of the chip, and should all be attached to VSS. PLL Ground--This pin supplies a quiet ground to the VCO to provide greater frequency stability. VSSPLL 2.3 Clock and Phase Lock Loop Signals Freescale Semiconductor, Inc... Table 6. PLL and Clock Signals Signal Name EXTAL Signal Type Input State During Reset Input Signal Description External Clock/Crystal Input--This input should be connected to an external clock or oscillator. After being squared, the input clock can be selected to provide the clock directly to the DSP core. The minimum instruction time is two input clock periods, broken up into four phases named T0, T1, T2, and T3. This input clock can also be selected as input clock for the on-chip PLL. Crystal Output--This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL should not be connected. Clock Output--This pin outputs a buffered clock signal. By programming the CS[1:0] bits in the PLL Control Register (PCR1), the user can select between outputting a squared version of the signal applied to EXTAL and a version of the DSP master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CS[1:0] bits in PCR1. External Filter Capacitor--This pin is used to add an external filter circuit to the Phase Lock Loop (PLL). Refer to Figure 9 on page 25. XTAL Output Chipdriven Chipdriven CLKO Output SXFC Input Input 2.4 Address, Data, and Bus Control Signals Table 7. Address Bus Signals Signal Name A0-A15 Signal Type Output State During Reset Tri-stated Signal Description Address Bus--A0-A15 change in T0, and specify the address for external program or data memory accesses. 10 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Address, Data, and Bus Control Signals Table 8. Data Bus Signals Signal Name D0-D15 Signa l Type Input/ Outpu t State During Reset Tri-stated Signal Description Data Bus--Read data is sampled in by the trailing edge of T2, while write data output is enabled by the leading edge of T2 and tri-stated by the leading edge of T0. D0-D15 are tri-stated when the external bus is inactive. Table 9. Bus Control Signals Freescale Semiconductor, Inc... Signal Name PS Signal Type Output State During Reset Tri-stated Signal Description Program Memory Select--PS is asserted low for external program memory access. If the external bus is not used during an instruction cycle (T0, T1, T2, T3), PS goes high in T0. Data Memory Select--DS is asserted low for external data memory access. If the external bus is not used during an instruction cycle (T0, T1, T2, T3), DS goes high in T0. Write Enable--WR is asserted during external memory write cycles. When WR is asserted low in T1, pins D0-D15 become outputs and the DSP puts data on the bus during the leading edge of T2. When WR is deasserted high in T3, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. Read Enable--RD is asserted during external memory read cycles. When RD is asserted low late T0/early T1, pins D0-D15 become inputs and an external device is enabled onto the DSP data bus. When RD is deasserted high in T3, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0-A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. DS Output Tri-stated WR Output Tri-stated RD Output Tri-stated DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. 2.5 Interrupt and Mode Control Signals Table 10. Interrupt and Mode Control Signals Signal Name MODA Signal Type Input State During Reset Input Signal Description Mode Select A--During hardware reset, MODA and MODB select one of the four initial chip operating modes latched into the Operating Mode Register (OMR). Several clock cycles (depending on PLL setup time) after leaving the Reset state, the MODA pin changes to external interrupt request IRQA. The chip operating mode can be changed by software after reset. External Interrupt Request A--The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If levelsensitive triggering is selected, an external pull up resistor is required for wiredOR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. Freescale Semiconductor, Inc... IRQA Input MODB Input Input Mode Select B/External Interrupt Request B--During hardware reset, MODA and MODB select one of the four initial chip operating modes latched into the Operating Mode Register (OMR). Several clock cycles (depending on PLL setup time) after leaving the Reset state, the MODB pin changes to external interrupt request IRQB. After reset, the chip operating mode can be changed by software. External Interrupt Request B--The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. IRQB Input RESET Input Input Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the MODA and MODB pins. The internal reset signal should be deasserted synchronous with the internal clocks. To ensure complete hardware reset, RESET and TRST/DE should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST/DE. 12 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. GPIO Signals 2.6 GPIO Signals Table 11. Programmable Interrupt GPIO Signals Signal Name PB0- PB7 Signal Type Input or Output State During Reset Input Signal Description Port B GPIO--These eight pins can be programmed to generate an interrupt for any pin programmed as an input when there is a transition on that pin. Each pin can individually be configured to recognize a low-to-high or a high-to-low transition. In addition, these pins are dedicated General Purpose I/O (GPIO) pins that can individually be programmed as input or output pins. Freescale Semiconductor, Inc... After reset, the default state is GPIO input. Table 12. Dedicated General Purpose Input/Output (GPIO) Signals Signal Name PB8- PB14 Signal Type Input or Output State During Reset Input Signal Description Port B GPIO--These seven pins are dedicated General Purpose I/O (GPIO) pins that can individually be programmed as input or output pins. After reset, the default state is GPIO input. XCOLF Input Input, pulled high internally XCOLF--During reset, the External Crystal Oscillator Low Frequency (XCOLF) function of this pin is active. PB15/XCOLF is tied to an on-chip pull-up transistor that is active during reset. When XCOLF is driven low during reset (or tied to a 10 k pull-down resistor), the crystal oscillator amplifier is set to a low frequency mode. In this low-frequency mode, only oscillator frequencies of 32 kHz and 38.4 kHz are supported. If XCOLF is not driven low during reset (or if a pull-down resistor is not used), the crystal oscillator amplifier operates in the Default mode, and oscillator frequencies from 2 MHz to 10 MHz are supported. If an external clock is provided to the EXTAL pin, 40 MHz is the maximum frequency allowed. (In this case, do not connect a pull-down resistor or drive this pin low during reset.) Port B GPIO--This pin is a dedicated GPIO pin that can individually be programmed as an input or output pin. After reset, the default state is GPIO input. PB15 Input or Output DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. 2.7 Serial Peripheral Interface (SPI) Signals Table 13. Serial Peripheral Interface (SPI0 and SPI1) Signals Signal Name MISO0 Signal Type Input/ Output State During Reset Input Signal Description SPI0 Master In/Slave Out (MISO0)--This serial data pin is an input to a master device and an output from a slave device. The MISO0 line of a slave device is placed in the high-impedance state if the slave device is not selected. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO 0 (PC0)--This pin is a GPIO pin called PC0 when the SPI MISO0 function is not being used. After reset, the default state is GPIO input. Freescale Semiconductor, Inc... PC0 Input or Output MOSI0 Input/ Output Input SPI0 Master Out/Slave In (MOSI0)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI0 line a half-cycle before the clock edge that the slave device uses to latch the data. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO 1 (PC1)--This pin is a GPIO pin called PC1 when the SPI MOSI0 function is not being used. After reset, the default state is GPIO input. PC1 Input or Output SCK0 Input/ Output Input SPI0 Serial Clock--This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the slave select pin is active low. In both master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO 2 (PC2)--This pin is a GPIO pin called PC2 when the SPI SCK0 function is not being used. After reset, the default state is GPIO input. PC2 Input or Output SS0 Input Input SPI0 Slave Select--This input pin selects a slave device before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. Port C GPIO 3 (PC3)--This pin is a GPIO pin called PC3 when the SPI SS0 function is not being used. After reset, the default state is GPIO input. PC3 Input or Output 14 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Signals Table 13. Serial Peripheral Interface (SPI0 and SPI1) Signals (Continued) Signal Name MISO1 Signal Type Input/ Output State During Reset Input Signal Description SPI1 Master In/Slave Out--This serial data pin is an input to a master device and an output from a slave device. The MISO1 line of a slave device is placed in the high-impedance state if the slave device is not selected. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO 4 (PC4)--This pin is a GPIO pin called PC4 when the SPI MISO1 function is not being used. After reset, the default state is GPIO input. PC4 Input or Output Freescale Semiconductor, Inc... MOSI1 Input/ Output Input SPI1 Master Out/Slave In (MOSI1)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI0 line a half-cycle before the clock edge that the slave device uses to latch the data. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO5 (PC5)--This pin is a GPIO pin called PC5 when the SPI MOSI1 function is not being used. After reset, the default state is GPIO input. PC5 Input or Output SCK1 Input/ Output Input SPI1 Serial Clock--This bidirectional pin provides a serial bit rate clock for the SPI. This gated clock signal is an input to a slave device and is generated as an output by a master device. Slave devices ignore the SCK signal unless the slave select pin is active low. In both master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. The driver on this pin can be configured as an open-drain driver by the SPI's WOM bit when this pin is configured for SPI operation. When using Wired-OR mode, the user must provide an external pull-up device. Port C GPIO 6 (PC6)--This pin is a GPIO pin called PC6 when the SPI SCK1 function is not being used. After reset, the default state is GPIO input. PC6 Input or Output SS1 Input Input SPI1 Slave Select--This input pin is used to select a slave device before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. Port C GPIO 7 (PC7)--This pin is a GPIO pin called PC7 when the SPI SS1 function is not being used. After reset, the default state is GPIO input. PC7 Input or Output DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. 2.8 Synchronous Serial Interface (SSI) Signals Table 14. Synchronous Serial Interface (SSI) Signals Signal Name STD Signal Type Output State During Reset Input Signal Description SSI Transmit Data (STD)--This output pin transmits serial data from the SSI Transmitter Shift Register. Port C GPIO 8 (PC8)--This pin is a GPIO pin called PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input. PC8 Input or Output Freescale Semiconductor, Inc... SRD Input Input SSI Receive Data--This input pin receives serial data and transfers the data to the SSI Receive Shift Register. Port C GPIO 9 (PC9)--This pin is a GPIO pin called PC9 when the SSI SRD function is not being used. After reset, the default state is GPIO input. PC9 Input or Output STCK Input/ Output Input SSI Serial Transmit Clock--This bidirectional pin provides the serial bit rate clock for the Transmit section of the SSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in Synchronous mode. Port C GPIO 10 (PC10)--This pin is a GPIO pin called PC10 when the SSI STCK function is not being used. After reset, the default state is GPIO input. PC10 Input or Output STFS Input/ Output Input Serial Transmit Frame Sync--This bidirectional pin is used by the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used by both the transmitter and receiver in Synchronous mode. It is used to synchronize data transfer and can be an input or an output. Port C GPIO 11 (PC11)--This pin is a GPIO pin called PC11 when the SSI STFS function is not being used. This pin is not required by the SSI in Gated Clock mode. After reset, the default state is input. PC11 Input or Output SRCK Input/ Output Input SSI Serial Receive Clock--This bidirectional pin provides the serial bit rate clock for the Receive section of the SSI. The clock signal can be continuous or gated and can be used only by the receiver. Port C GPIO 12 (PC12)--This pin is a GPIO pin called PC12 when the SSI STD function is not being used. After reset, the default state is GPIO input. PC12 Input or Output 16 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Module Signals Table 14. Synchronous Serial Interface (SSI) Signals (Continued) Signal Name SRFS Signal Type Input/ Output State During Reset Input Signal Description Serial Receive Frame Sync (SRFS)--This bidirectional pin is used by the Receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used only by the receiver. It is used to synchronize data transfer and can be an input or an output. Port C GPIO 13 (PC13)--This pin is a GPIO pin called PC13 when the SSI SRFS function is not being used. After reset, the default state is GPIO input. PC13 Input or Output Freescale Semiconductor, Inc... 2.9 Timer Module Signals Table 15. Timer Module Signals Signal Name TIO01 Signal Type Input/ Output State During Reset Input Signal Description Timer 0 and Timer 1 Input/Output (TIO01)--This bidirectional pin receives external pulses to be counted by either the on-chip 16-bit Timer 0 or Timer 1 when configured as input and external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. When configured as output, it generates pulses or toggles on a Timer 0 or Timer 1 overflow event. Selection of Timer 0 or Timer 1 is programmable through an internal register. Port C GPIO 14 (PC14)--This pin is a GPIO pin called PC14 when the Timer TIO01 function is not being used. After reset, the default state is GPIO input. PC14 Input or Output TIO2 Input/ Output Input Timer 2 Input/Output (TIO2)--This bidirectional pin receives external pulses to be counted by the on-chip 16-bit Timer 2 when configured as input and external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. When configured as output, it generates pulses or toggles on a Timer 2 overflow event. Port C GPIO 15 (PC15)--This pin is a GPIO pin called PC15 when the Timer TIO2 function is not being used. After reset, the default state is GPIO input. PC15 Input or Output DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. 2.10 JTAG/OnCETM Port Signals Table 16. JTAG/On-Chip Emulation (OnCE) Signals Signal Name TCK Signal Type Input State During Reset Signal Description Input, Test Clock Input--This input pin provides a gated clock to synchronize the test pulled low logic and shift serial data to the JTAG/OnCE port. The pin is connected internally internally to a pull-down resistor. Input, Test Mode Select Input--This input pin is used to sequence the JTAG TAP pulled high controller's state machine. It is sampled on the rising edge of TCK and has an internally on-chip pull-up resistor. Input, Test Data Input--This input pin provides a serial input data stream to the pulled high JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip internally pull-up resistor. Tri-stated Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. TMS Input Freescale Semiconductor, Inc... TDI Input TDO Output TRST Input DE Output Input, Test Reset--As an input, a low signal on this pin provides a reset signal to the pulled high JTAG TAP controller. internally Debug Event--When programmed within the OnCE port as an output, DE provides a low pulse on recognized debug events; when configured as an output signal, the TRST input is disabled. To ensure complete hardware reset, TRST/DE should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST/DE. This pin is connected internally to a pull-up resistor. 18 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Characteristics Part 3 Specifications 3.1 General Characteristics The DSP56824 is fabricated in high-density CMOS with Transistor-Transistor Logic (TTL)-compatible inputs, 5-volt tolerant Input/Output (I/O), and CMOS-compatible outputs. Absolute maximum ratings given in Table 17 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56824 dc/ac electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. WARNING: Freescale Semiconductor, Inc... This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either or VCC or GND). Table 17. Absolute Maximum Ratings (GND = 0 V) Rating Supply voltage All other input voltages Current drain per pin excluding VDD and GND Storage temperature range Symbol VDD VIN I TSTG Value -0.3 to 4.0 (GND - 0.3) to (VDD + 0.3) 10 -55 to 150 Unit V V mA C Table 18. Recommended Operating Conditions Characteristic Supply voltage Ambient temperature Symbol VDD TA Value 2.7 to 3.6 -40 to 85 Unit V C DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. Table 19. Package Thermal Characteristics 100-pin TQFP Thermal Resistance1 Symbol Junction-to-ambient (estimated)2 Junction-to-case (estimated)3 RJC Value 65 10 Unit C/W C/W Freescale Semiconductor, Inc... 1. See discussion under Section 5, "Design Considerations," on page 58. 2. Junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided Printed Circuit Board per SEMI G38-87 in natural convection. SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Road, Mountain View, CA 94043, (415) 964-5111. 3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88 with the exception that the cold plate temperature is used for the case temperature. 3.2 DC Electrical Characteristics Table 20. DC Electrical Characteristics Characteristics Supply voltage Input high voltage: EXTAL All other inputs Input low voltage EXTAL All other inputs Input leakage current @ 2.4 V/0.4 V with VDD = 3.6 V Input/output tri-state (off-state) leakage current @ 2.4 V/ 0.4 V with VDD = 3.6 V Output high voltage IOH = -0.3 mA IOH = -50 A Output low voltage IOL = 2 mA IOL = 50 A) Core CPU supply current1 (FPLL = 70 MHz) Stop mode current1,2 Input capacitance (estimated) Symbol VDD Min 2.7 Typ -- Max 3.6 Unit V V -- -- VDD VIHC VIH 0.8 x VDD 2.0 VILC VIL IIN ITSI -0.3 -0.3 -1 -10 -- -- -- -- 0.2 x VDD 0.8 1 +10 V A A VOH VDD - 0.7 VDD - 0.3 VOL -- -- ICORE ISTOP CIN -- -- -- -- -- 20 2 10 0.4 0.2 30 5 -- -- -- -- -- V V mA A pF 1. To obtain these results, all inputs must be terminated (i.e., not allowed to float) using CMOS levels. 2. At 25C, VDD = 3.0 V, VIH = VDD, VIL = 0 V, output pin XTAL disconnected with external clocks applied on EXTAL pin and inputs to Data Bus are static valid. 20 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AC Electrical Characteristics 3.3 AC Electrical Characteristics (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Timing waveforms in Section 3.3, "AC Electrical Characteristics," are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V for all pins except EXTAL, which is tested using the input levels in Section 3.2, "DC Electrical Characteristics." Figure 3 shows the levels of VIH and VIL for an input signal. Pulse Width VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH - VIL)/2. AA1447 Low High 90% 50% 10% Freescale Semiconductor, Inc... VIL Rise Time Figure 3. Input Signal Measurement References Figure 4 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven , and enters a low impedance state. Tristated, when a bus or signal is placed in a high impedance state. Data Valid state, when a signal level has reached VOL orVOH. Data Invalid state, when a signal level is in transition between VOL and VOH. Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tristated Data3 Valid Data3 Data Active AA1448 Figure 4. Signal States DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. 3.4 External Clock Operation (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) The DSP56824 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. Figure 5 shows the transconductance model for XTAL. Table 21 shows the electrical characteristics for EXTAL and XTAL pins. Vout Vin x gm ro Vin Vout AA0118 Freescale Semiconductor, Inc... Figure 5. XTAL Transconductance Model Table 21. EXTAL/XTAL Electrical Characteristics Characteristics EXTAL peak-to-peak swing (for any value of XCOLF) VDDPLL = 2.7 V VDDPLL = 3.0 V VDDPLL = 3.6 V XTAL transconductance XCOLF = 0 XCOLF = VDD XTAL output resistance XCOLF = 0 XCOLF = VDD Symbol Min Typ Max Unit -- -- -- gm 1.27 1.38 1.58 -- -- -- 1.9 2.1 2.75 V p-p V p-p V p-p 0.206 2.06 ro 28.3 2.83 0.465 4.65 1.02 10.2 mA/V mA/V 80.6 8.06 209.4 20.94 k k The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 22. Figure 6 shows typical crystal oscillator circuits. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. When using the on-chip oscillator in conjunction with an external crystal to generate the DSP clock, the following specifications apply. When driving the clock directly into EXTAL (not using a crystal), the input clock should follow normal digital DSP56824 requirements. 22 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Clock Operation Crystal Frequency = 32 kHz or 38.4 kHz XCOLF = 0 Crystal Frequency = 2-10 MHz XCOLF = 1 EXTAL XTAL Rx Rx = 10 M, Ry = 330 k Cw = 12 pF, Cx = 19 pF EXTAL XTAL Rz Rz = 10 M Cy, Cz = 31 pF Cw Example Crystal Parameters: Motional capacitance, C = 2.3 fF Ry Motional inductance, L 1 7.47 kH 1= Series resistance, RS = 36 k Shunt capacitance, C0 = 1 pF Cx Load capacitance, CL = 12 pF (Assumes pin and trace capacitance on the EXTAL and XTAL pins is 9 pF each) Cy Example Crystal Parameters: Series resistance, RS = 36 k Shunt capacitance, C0 = 7 pF Load capacitance, CL = 20 pF (Assumes pin and trace Cz capacitance on the EXTAL and XTAL pins is 9 pF each) AA0180 Freescale Semiconductor, Inc... Figure 6. Examples of Crystal Oscillator Circuits If the design uses an external clock circuit, apply the external clock input to the EXTAL input with the XTAL pin left unconnected, as shown in Figure 7. DSP56824 EXTAL XTAL Not External Clock Connected AA1449 Figure 7. Connecting an External Clock Signal Table 22. Clock Operation Timing 70 MHz No. Characteristics Min 1 2 3 4 Frequency of operation (external clock) Clock cycle time Instruction cycle time External reference frequency Crystal option, XCOLF = 0 External clock option, XCOLF = 1 External clock input rise time External clock input fall time External clock input high time External clock input low time PLL output frequency 0 14.29 28.57 Max 70 -- -- MHz ns ns Unit .032 0 -- -- 6.5 6.5 10 10 70 3 3 -- -- 70 MHz MHz ns ns ns ns MHz 5 6 7 8 9 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. Table 22. Clock Operation Timing (Continued) 70 MHz No. Characteristics Min 10 1. PLL stabilization time after crystal oscillator start-up time1 -- Max 10 ms Unit This is the minimum time required after the PLL setup is changed to ensure reliable operation 3 External Clock 90% 50% 10% VIH 90% 50% 10% Freescale Semiconductor, Inc... 7 2 Note: The midpoint is VIL + (VIH - VIL)/2. 8 6 5 VIL AA0182 Figure 8. External Clock Timing 3.5 External Components for the PLL The on-chip PLL requires an extra circuit connected to the SXFC pin, as shown in Figure 9. As indicated in Table 23, the values of R, C1, and C should be chosen based on the Multiplication Factor used to derive the desired operating frequency from the input frequency selected. This circuit affects the performance of the PLL. Table 23. Recommended Component Values for PLL Multiplication Factors Multiplication Factor 1024 512 256 128 100 80 40 10 4 2 Cl 10 nF 2.7 nF 2.7 nF 2.7 nF 2.7 nF 2.7 nF 2.7 nF 2.7 nF 250 pF 250 pF R 5 k 5 k 5 k 2 k 2 k 2 k 2 k 2 k 1 k 1 k C 15 nF 15 nF 15 nF 15 nF 15 nF 15 nF 15 nF 15 nF 15 nF 15 nF 24 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. External Components for the PLL Table 23. Recommended Component Values for PLL Multiplication Factors Multiplication Factor Cl R C Note: Because of the high number of Multiplication Factors available, these are the only Multiplication Factors evaluated. SXFC VDDPLL VSSPLL Freescale Semiconductor, Inc... R 0.01 F Cl C AA0836 0.1 F Figure 9. Schematic of Required External Components for the PLL DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. 3.6 Port A External Bus Synchronous Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) 3.6.1 Capacitance Derating The DSP56824 external bus synchronous timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the pins A0-A15, D0-D15, PS, DS, RD, and WR derates linearly at 1.7 ns per 20 pF of additional capacitance from 50 pF to 250 pF of loading. The CLKO pin drive capability is 20 pF. When an internal memory access follows an external memory access, the PS, DS, RD, and WR strobes remain deasserted and A0-A15 do not change from their previous state. NOTE: Freescale Semiconductor, Inc... In Figure 10 and Figure 11, T0, T1, T2, and T3 refer to the internal clock phases and TW refers to wait state. Table 24. External Bus Synchronous Timing No 20 Characteristic External Input Clock High to CLKO High XCO Asserted High XCO Asserted Low CLKO High to A0-A15 Valid CLKO High to PS, DS Valid CLKO Low to WR Asserted Low CLKO High to RD Asserted Low CLKO High to D0-D15 Out Valid CLKO High to D0-D15 Out Invalid D0-D15 In Valid to CLKO Low (Setup) CLKO Low to D0-D15 Invalid (Hold) CLKO Low to WR Deasserted CLKO Low to RD Deasserted WR Hold Time from CLKO Low RD Hold Time from CLKO Low CLKO High to D0-D15 Out Active CLKO High to D0-D15 Out Tri-state CLKO High to A0-A15 Invalid CLKO High to PS, DS Invalid Min Max Unit ns 3.4 9.0 0.9 0.3 1.1 0.4 0.9 0.2 0.6 0.7 1.9 1.8 0.2 0.2 -1.3 -- -0.9 -0.7 13.8 18.5 2.0 3.1 6.4 4.8 3.1 0.3 -- -- -- -- -- -- 0.6 0.3 -2.6 -1.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 26 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port A External Bus Synchronous Timing Internal Clock Phases External Clock (Input) CLKO (Output) 21 A0-A15 (See Note) 35 T0 T1 T2 T3 T0 T1 T2 T3 T0 20 Freescale Semiconductor, Inc... 22 PS, DS 23 WR (Output) 24 RD (Output) 32 25 D0-D15 (Output) 33 27 D0-D15 (Input) Data In 28 Data Out 30 29 31 36 26 34 Note: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. AA1450 Figure 10. Synchronous Timing--No Wait State DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. Internal Clock Phases External Clock (Input) CLKO (Output) 21 A0-A15 (See Note) 35 T0 T1 T2 TW T2 TW T2 T3 T0 20 Freescale Semiconductor, Inc... 22 PS, DS 23 WR (Output) 24 RD (Output) 31 36 29 30 32 25 D0-D15 (Output) 33 D0-D15 (Input) Data Out 28 27 Data In 34 26 ote: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. AA0184 Figure 11. Synchronous Timing--Two Wait States 28 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port A External Bus Asynchronous Timing 3.7 Port A External Bus Asynchronous Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 25. External Bus Asynchronous Timing No. 40 41 Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states > 0 WR Asserted to D0-D15 Out Valid Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Input Data Hold to RD Deasserted RD Assertion Width Wait states = 0 Wait states > 0 Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Min T - 0.5 Max -- Unit ns 2T - 6.4 2T(WS + 1) - 6.4 -- T - 5.6 -- -- T + 0.7 -- ns ns ns ns Freescale Semiconductor, Inc... 42 43 44 T + 0.2 T(2WS + 1) + 0.2 T - 5.6 3T + 0.3 2.6 -- -- -- -- -- ns ns ns ns ns 45 46 47 48 3T - 5.8 2T(WS) + 3T - 5.8 -- -- ns ns 49 -- -- 3T - 5.4 2T(WS) + 3T - 5.4 -- ns ns 50 51 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 0.0 ns -- -- 3T - 4.7 2T(WS) + 3T - 4.7 -- -- -- -- ns ns 52 53 54 55 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted T - 0.9 T - 0.8 2T - 1.0 2T - 0.8 ns ns ns ns Note: Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = 1/2 the clock cycle. For 70 MHz operation, T = 7.14 ns. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. A0-A15, PS, DS (See Note) 50 46 45 48 53 RD 40 54 41 52 51 42 44 Data Out 49 43 Data In 47 55 WR Freescale Semiconductor, Inc... D0-D15 Note: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. AA1451 Figure 12. External Bus Asynchronous Timing 3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 26. Reset, Stop, Wait, Mode Select, and Interrupt Timing 70 MHz No. Characteristics Min 60 RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 Asynchronous RESET Deassertion to First External Address Output 3 Synchronous Reset Setup Time from RESET Deassertion to CLKO Low Synchronous Reset Delay Time from CLKO High to the First External Access3 Mode and XCOLF Select Setup Time 1 Unit Max 1 4.6 14.0 ns 61 524,329 + 38 T 38T 67T + 4.5 -- -- ns ns 62 67T + 12.3 ns 63 3.8 5.6 ns 64 66T + 2.5 66T + 7.5 ns 65 0.3 -- ns 30 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 26. Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued) 70 MHz No. Characteristics Min1 66 67 68 Mode and XCOLF Select Hold Time Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine Synchronous setup time from IRQA, IRQB assertion to Synchronous CLKO High4, 5 CLKO Low to First Interrupt Vector Address Out Valid after Synchronous recovery from Wait State6 IRQA Width Assertion to Recover from Stop State7 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) 2 OMR Bit 6 = 0 OMR Bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop)2 OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop)2 OMR Bit 6 = 0 OMR Bit 6 = 1 0 2T + 3.8 28 + 2.5 Max1 -- -- -- ns ns ns Unit 69 31T + 3.7 -- ns Freescale Semiconductor, Inc... 70 1.9 2T ns 71 24T + 4.4 -- ns 72 73 2T + 3.8 -- ns 524,329T 22T -- -- ns ns 74 524,329T 22T -- -- ns ns 75 524,336T + 2. 5 22T + 2.5 -- -- ns ns 1. In the formulas, T = 1/2 the clock cycle and WS = the number of wait states. For an internal frequency of 70 MHz, T = 7.14 ns. 2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state 3. The instruction fetch is visible on the pins only in Mode 2 and Mode 3. 4. Timing No. 72 is for all IRQx interrupts, while timing No. 73 is only when exiting the Wait state. 5. Timing No. 72 triggers off T0 in the Normal state and off phi0 when exiting the Wait state. 6. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 7. The interrupt instruction fetch is visible on the pins only in Mode 3. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. RESET 61 60 A0-A15, D0-D15 PS, DS, RD, WR 62 First Fetch First Fetch AA1452 Figure 13. Asynchronous Reset Timing Freescale Semiconductor, Inc... CLKO 63 RESET 64 A0-A15, PS, DS, RD, WR AA0187 Figure 14. Synchronous Reset Timing RESET 65 66 MODA, MODB, XCOLF IRQA, IRQB, PB15 AA0188 Figure 15. Operating Mode Select Timing IRQA, IRQB 67 AA0189 Figure 16. External Interrupt Timing (Negative-Edge-Sensitive) 32 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Reset, Stop, Wait, Mode Select, and Interrupt Timing A0-A15, PS, DS, RD, WR First Interrupt Instruction Execution 68 IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin Freescale Semiconductor, Inc... 69 IRQA, IRQB b) General Purpose I/O AA0190 Figure 17. External Level-Sensitive Interrupt Timing CLKO T0, T2 phi0 70 T1, T3 phi1 IRQA, IRQB 71 A0-A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch AA0191 Figure 18. Synchronous Interrupt from Wait State Timing DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 33 Freescale Semiconductor, Inc. 72 IRQA 73 A0-A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector AA0192 Figure 19. Recovery from Stop State Using Asynchronous Interrupt Timing Freescale Semiconductor, Inc... 74 IRQA 75 A0-A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch AA0193 Figure 20. Recovery from Stop State Using IRQA Interrupt Service 3.9 Port B and C Pin GPIO Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 27. GPIO Timing No. 80 81 82 83 84 Characteristics CLKO high to GPIO out valid (GPIO out delay time) 2 Min1 -- 1.5 7.8 0.5 12T - 1.7 Max1 10.7 -- -- -- -- Unit ns ns ns ns ns CLKO high to GPIO out not valid (GPIO out hold time) GPIO in valid to CLKO high (GPIO in set-up time) CLKO high to GPIO in not valid (GPIO in hold time) Fetch to CLKO high before GPIO change 34 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Port B and C Pin GPIO Timing Table 27. GPIO Timing (Continued) No. 85 86 Characteristics Port B interrupt pulse width Port B interrupt assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine Port B interrupt assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine Min1 4T Max1 -- Unit ns 19T + 9.6 -- ns 87 31T + 10. 8 -- ns Freescale Semiconductor, Inc... 1. In the formulas, T = 1/2 the clock cycle. For an internal frequency of 70 MHz, T = 7.14 ns. 2. If a 10 kW pullup or pulldown resistor is connected to XCOLF/PB15, add 3.9 ns for timings on XCOLF/PB15. CLKO (Output) 80 81 GPIO (Output) 82 83 GPIO (Input) VALID A0-A15 84 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. AA0194 Figure 21. GPIO Timing Port B GPIO Interrupt (Input) 85 AA0195 Figure 22. Port B Interrupt Timing (Negative-Edge-Sensitive) DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 35 Freescale Semiconductor, Inc. A0-A15, PS, DS, RD, WR First Interrupt Instruction Execution 86 Port B GPIO Interrupt (Input) a) First Interrupt Instruction Execution General Purpose I/O Pin Freescale Semiconductor, Inc... Port B GPIO Interrupt (Input) 87 b) General Purpose I/O AA0196 Figure 23. Port B GPIO Interrupt Timing 3.10 Serial Peripheral Interface (SPI) Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C) Table 28. SPI Timing 70 MHz No. Characteristic 20 pF Output Load Min 90 Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Max 50 pF Output Load Min Max Unit 100 100 -- -- 100 100 -- -- ns ns 91 -- 6.8 -- -- -- 25 -- -- ns ns 92 -- 6.5 -- -- -- 100 -- -- ns ns ns ns 93 17.6 25 -- -- 17.6 25 -- -- 94 24.1 25 -- -- 24.1 25 -- -- ns ns 36 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Timing Table 28. SPI Timing (Continued) 70 MHz No. Characteristic 20 pF Output Load Min 95 Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to highimpedance state) Slave Data Valid Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave Max 50 pF Output Load Min Max Unit 15.6 -3.2 -- -- 20 0 -- -- ns ns 96 Freescale Semiconductor, Inc... 0 0 -- -- 0 0 -- -- ns ns 97 4.8 10.7 4.8 15 ns ns 98 3.7 15.2 3.7 15.2 ns ns 99 4.5 4.6 3.5 20.4 4.5 4.6 3.5 20.4 ns ns 100 0 0 -- -- 0 0 -- -- ns ns 101 4.1 0 5.5 4.0 4.1 0 11.5 10.0 ns ns 102 1.5 0 4.7 4.0 2.0 2.0 9.7 9.0 ns ns DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 37 Freescale Semiconductor, Inc. SS (Input) SS is held High on master 90 101 94 102 SCK (CPL = 0) (Output) See Note 93 94 SCK (CPL = 1) (Output) See Note 102 101 Freescale Semiconductor, Inc... 96 95 MISO (Input) 99 (ref) MOSI (Output) MSB in 100 Master MSB out 102 Note: Bits 6-1 93 Bits 6-1 99 LSB in 100 (ref) Master LSB out 101 AA0197 This first clock edge is generated internally, but is not seen at the SCK pin. Figure 24. SPI Master Timing (CPH = 0) 38 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Timing SS (Input) 90 SS is held High on master 102 94 101 See Note SCK (CPL = 0) (Output) 93 94 SCK (CPL = 1) (Output) 93 95 101 MISO (Input) 99 (ref) MOSI (Output) MSB in 100 Master MSB out 102 Note: Bits 6-1 99 Bits 6 - 1 LSB in 100(ref) Master LSB out 101 102 See Note Freescale Semiconductor, Inc... 96 This last clock edge is generated internally, but is not seen at the SCK pin. AA0198 Figure 25. SPI Master Timing (CPH = 1) DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 39 Freescale Semiconductor, Inc. SS (Input) 90 94 SCK (CPL = 0) (Input) 93 91 SCK (CPL = 1) (Input) 97 93 101 Bits 6-1 99 96 MOSI (Input) Note: MSB in Bits 6-1 102 98 Slave LSB out 100 LSB in AA0199 See Note 102 101 92 94 Freescale Semiconductor, Inc... MISO (Output) 95 Slave MSB out 100 Not defined, but normally MSB of character just received Figure 26. SPI Slave Timing (CPH = 0) 40 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) Timing SS (Input) 90 94 K (CPL = 0) (Input) 93 91 94 K (CPL = 1) (Input) 99 93 97 MISO (Output) See Note 102 101 92 101 102 Bits 6-1 99 96 98 Slave LSB out 100 LSB in AA0200 Freescale Semiconductor, Inc... Slave MSB out 95 MOSI (Input) Note: MSB in Bits 6-1 Not defined, but normally LSB of character previously transmitted Figure 27. SPI Slave Timing (CPH = 1) 3.11 Synchronous Serial Interface (SSI) Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 29. SSI Timing 70 MHz No. Characteristic Min Internal Clock Operation 110 111 112 113 114 115 116 Clock cycle2 Clock high period Clock low period Output clock rise/fall time STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 100 33.2 30.6 -- 1.8 1.3 -2.9 -- -- -- 7.5 9.7 10 8 i ck i ck i ck i ck i ck i ck i ck ns ns ns ns ns ns ns Max Case1 Unit DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 41 Freescale Semiconductor, Inc. Table 29. SSI Timing (Continued) 70 MHz No. Characteristic Min 117 118 119 120 121 122 123 124 125 126 127 SRCK high to SRFS (bl) low3 SRD setup time before SRCK low SRD hold time after SRCK low STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 STCK high to STD enable from high impedance STCK high to STD valid STCK High to STD not valid STCK high to STD high impedance External Clock Operation 128 129 130 132 133 134 135 136 137 138 139 140 141 Clock cycle2 Clock high period Clock low period SRD Setup time before SRCK low SRD hold time after SRCK low4 STCK high to STFS (bl) high3 SRCK high to SRFS (bl) high3 STCK high to STFS (bl) low3 SRCK high to SRFS (bl) low3 STCK high to STFS (wl) high3 SRCK high to SRFS (wl) high3 STCK high to STFS (wl) low3 SRCK high to SRFS (wl) low3 100 50 50 -8.7 1.7 0.4 0.5 0 0 0.4 0.5 0 0 -- -- -- -- -- 100 100 99 99 100 100 99 99 x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck x ck ns ns ns ns ns ns ns ns ns ns ns ns ns -2.7 9 0 13.8 14.5 -2.9 -2.2 1.5 -3.4 -5.7 6.8 Max 8.7 -- -- 24.4 25.9 9.0 10.6 1.7 7.9 0.7 11.3 i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck i ck ns ns ns ns ns ns ns ns ns ns ns Case1 Unit Freescale Semiconductor, Inc... 42 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) Timing Table 29. SSI Timing (Continued) 70 MHz No. Characteristic Min 142 143 144 145 STCK high to STD enable from high impedance STCK high to STD valid STCK high to STD not valid STCK high to STD high impedance 7.8 11.7 5.8 9.2 Max 19 28.5 21.1 22.9 x ck x ck x ck x ck ns ns ns ns Case1 Unit Freescale Semiconductor, Inc... Synchronous Internal Clock Operation (in addition to standard internal clock parameters) 146 147 SRD setup before STCK falling SRD hold after STCK falling4 18.4 0 -- -- i ck s i ck s ns ns Synchronous External Clock Operation (in addition to standard external clock parameters) 148 149 1. SRD setup before STCK falling SRD hold after STCK falling4 -4.7 1.7 -- -- x ck s x ck s ns ns The following abbreviations are used to represent the various operational cases: i ck = Internal Clock and Frame Sync x ck = External Clock and Frame Sync i ck s = Internal Clock, Synchronous mode (implies that only one frame sync FS is used) x ck s = External Clock, Synchronous mode (implies that only one frame sync FS is used) 2. All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP = 0 in CRB) and a noninverted frame sync (FSI = 0 in CRB). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables and in the figures. 3. bl = bit length; wl = word length. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 43 Freescale Semiconductor, Inc. 110 113 111 STCK Output 114 STFS (bl) Output 120 122 116 112 Freescale Semiconductor, Inc... STFS (wl) Output 125 124 STD Output 146 SRD Input Note: SRD Input in Synchronous mode only 126 127 First Bit 147 First Bit Last Bit Last Bit AA0201 Figure 28. SSI Transmitter Internal Clock Timing 44 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) Timing 128 129 STCK Input 134 STFS (bl) Input 138 140 136 130 Freescale Semiconductor, Inc... STFS (wl) Input 143 142 STD Output 148 SRD Input Note: SRD Input in Synchronous mode only 144 145 First Bit 149 First Bit Last Bit Last Bit AA0202 Figure 29. SSI Transmitter External Clock Timing DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 45 Freescale Semiconductor, Inc. 110 113 111 SRCK Output 115 SRFS (bl) Output 121 123 117 112 Freescale Semiconductor, Inc... RFS (wl) Output 119 118 SRD Input First Bit Last Bit AA0203 Figure 30. SSI Receiver Internal Clock Timing 128 129 SRCK Input 135 SRFS (bl) Input 139 SRFS (wl) Input 133 132 SRD Input First Bit Last Bit AA0204 130 137 141 Figure 31. SSI Receiver External Clock Timing 46 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Timer Timing 3.12 Timer Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 30. Timer Timing 70 MHz No. Characteristic Min 150 151 152 Timer input valid to CLKO high (setup time) CLKO high to timer input not valid (hold time) CLKO high to timer output asserted CLKO high to timer output deasserted Timer input period Timer input high/low period 11.4 0 9.5 5.1 8T 4T Max -- -- 18.7 20.7 -- -- ns ns ns ns ns ns Unit Freescale Semiconductor, Inc... 153 154 155 CLKO (Output) 150 TIO01 TIO2 (Input) 152 TIO01 TIO2 (Output) 153 151 TIO01 TIO2 (Input) 154 155 155 AA0205 Figure 32. Timer Timing DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 47 Freescale Semiconductor, Inc. 3.13 JTAG Timing (VSS = 0 V, VDD = 2.7-3.6 V, TA = -40 to +85C, CL = 50 pF) Table 31. JTAG Timing 70 MHz No. Characteristics Min 160 TCK frequency of operation In OnCE Debug mode (EXTAL/8) In JTAG mode TCK cycle time TCK clock pulse width Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output tri-state TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Max Unit 0.0 0.0 100 50 34.5 0 -- -- 0.4 1.2 -- -- 50 8T 8.75 10 -- -- -- -- 40.6 43.4 -- -- 26.6 23.5 -- -- MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns Freescale Semiconductor, Inc... 161 162 164 165 166 167 168 169 170 171 172 173 Note: Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = 1/2 the clock cycle. For 70 MHz operation, T = 7.14 ns. 161 VIH 162 VM VIL 162 VM TCK (Input) VM = VIL + (VIH - VIL)/2 AA1453 Figure 33. Test Clock Input Timing Diagram 48 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. JTAG Timing TCK (Input) 164 Data Inputs 166 Data Outputs 167 Output Data Valid Input Data Valid 165 Freescale Semiconductor, Inc... Data Outputs 166 Data Outputs Output Data Valid AA0207 Figure 34. Boundary Scan (JTAG) Timing Diagram TCK (Input) 168 TDI TMS (Input) 170 TDO (Output) 171 TDO (Output) 170 TDO (Output) Output Data Valid AA0208 169 Input Data Valid Output Data Valid Figure 35. Test Access Port Timing Diagram DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 49 Freescale Semiconductor, Inc. TRST (Input) 172 AA0209 Figure 36. TRST Timing Diagram Freescale Semiconductor, Inc... DE 173 AA0210 Figure 37. OnCE--Debug Event 50 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Package and Pin-Out Information Part 4 Packaging 4.1 Package and Pin-Out Information This section contains package and pin-out information for the 100-pin Thin Quad Flat Pack (TQFP) configuration of the DSP56824. VSS CLKO PB15/XCOLF PB14 PB13 PB12 VDD VSS PB11 PB10 PB9 PB8 PB7 PB6 PB5 VSS VDD PB4 PB3 PB2 PB1 PB0 MODA/IRQA MODB/IRQB RESET Freescale Semiconductor, Inc... 75 RD A15 A14 A13 A12 A11 A10 A9 VDD VSS A8 A7 A6 A5 VSS VDD PS DS VSS VDD A4 A3 A2 A1 A0 25 XTAL EXTAL VDD SXFC VDDPLL VSSPLL PC0/MISO0 PC1/MOSI0 PC2/SCK0 PC3/SS0 PC4/MISO1 PC5/MOSI1 PC6/SCK1 VSS VDD PC7/SS1 PC8/STD PC9/SRD PC10/STCK PC11/STFS PC12/SRCK PC13/SRFS PC14/TIO01 PC15/TIO2 WR 76 51 50 Orientation Mark 100 1 (Top View) 26 TDI TRST/DE TCK TMS TDO D15 D14 VDD VSS D13 D12 D11 D10 D9 D8 D7 D6 D5 VSS VDD D4 D3 D2 D1 D0 AA1454 Figure 38. Top View, DSP56824 100-pin TQFP Package DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 51 Freescale Semiconductor, Inc. 51 Freescale Semiconductor, Inc... 25 TDI TRST/DE TCK TMS TDO D15 D14 VDD VSS D13 D12 D11 D10 D9 D8 D7 D6 D5 VSS VDD D4 D3 D2 D1 D0 50 75 76 RESET MODB/IRQB MODA/IRQA PB0 PB1 PB2 PB3 PB4 VDD VSS PB5 PB6 PB7 PB8 PB9 PB10 PB11 VSS VDD PB12 PB13 PB14 PB15/XCOLF CLKO VSS Orientation Mark 26 (Bottom View) 100 1 XTAL EXTAL VDD SXFC VDDPLL VSSPLL PC0/MISO0 PC1/MOSI0 PC2/SCK0 PC3/SS0 PC4/MISO1 PC5/ MOSI1 PC6/ SCK1 VSS VDD PC7/SS1 PC8/STD PC9/SRD PC10/STCK PC11/STFS PC12/SRCK PC13/SRFS PC14/TIO01 PC15/TIO2 WR A0 A1 A2 A3 A4 VDD VSS DS PS VDD VSS A5 A6 A7 A8 VSS VDD A9 A10 A11 A12 A13 A14 A15 RD AA1455 Figure 39. Bottom View, DSP56824 TQFP Package 52 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Package and Pin-Out Information Table 32. DSP56824 Pin Identification by Pin Number 100-pin Package Pin # 1 2 3 4 5 Signal Name RD A15 A14 A13 A12 A11 A10 A9 VDD VSS A8 A7 A6 A5 VSS VDD PS DS VSS VDD A4 A3 A2 A1 A0 100-pin Package Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name D0 D1 D2 D3 D4 VDD VSS D5 D6 D7 D8 D9 D10 D11 D12 D13 VSS VDD D14 D15 TDO TMS TCK TRST/DE TDI 100-pin Package Pin # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name 100-pin Package Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name RESET MODB/IRQB MODA/IRQA PB0 PB1 PB2 PB3 PB4 VDD VSS PB5 PB6 PB7 PB8 PB9 PB10 PB11 VSS VDD PB12 PB13 PB14 XCOLF/PB15 CLKO VSS XTAL EXTAL VDD SXFC VDDPLL VSSPLL PC0/MISO0 PC1/MOSI0 PC2/SCK0 PC3/SS0 PC4/MISO1 PC5/MOSI1 PC6/SCK1 VSS VDD PC7/SS1 PC8/STD PC9/SRD PC10/STCK PC11/STFS PC12/SRCK PC13/SRFS PC14/TIO01 PC15/TIO2 WR Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 53 Freescale Semiconductor, Inc. Table 33. DSP56824 Pin Identification by Signal Name Signal Name A0 A1 A2 A3 A4 A5 Pin # 25 24 23 22 21 14 13 12 11 8 7 6 5 4 3 2 74 26 27 28 29 30 33 34 35 36 37 Signal Name D13 D14 D15 DE DS EXTAL IRQA IRQB MISO0 MISO1 MODA MODB MOSI0 MOSI1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 Pin # 41 44 45 49 18 77 53 52 82 86 53 52 83 87 54 55 56 57 58 61 62 63 64 65 66 67 70 Signal Name PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PS RD RESET SCK0 SCK1 SRFS SRCK SRD SS0 SS1 STCK Pin # 82 83 84 85 86 87 88 91 92 93 94 95 96 97 98 99 17 1 51 84 88 97 96 93 85 91 94 Signal Name TCK TDI TD0 TIO01 TIO2 TMS TRST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPLL Pin # 48 50 46 98 99 47 49 9 16 20 31 43 59 69 78 90 80 10 15 19 32 42 60 68 75 89 81 Freescale Semiconductor, Inc... A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CLKO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 54 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Package and Pin-Out Information Table 33. DSP56824 Pin Identification by Signal Name (Continued) Signal Name D10 D11 D12 Pin # 38 39 40 Signal Name PB13 PB14 PB15 Pin # 71 72 73 Signal Name STD STFS SXFC Pin # 92 95 79 Signal Name WR XCOLF XTAL Pin # 100 73 76 Table 34. DSP56824 Power Supply Pins Pin # Power Signal VDD VDD VSS VSS VDD VDD VSS VSS VDDPLL VSSPLL PLL Data Bus Buffers Circuits Supplied Address Bus Buffers and Bus Control Pin # 16 69 15 68 59 78 90 60 75 89 Power Signal VDD VDD VSS VSS VDD VDD VDD VSS VSS VSS Clock, Bus Control, Port B, Port C , and JTAG/ OnCE Port Circuits Supplied Internal Logic Freescale Semiconductor, Inc... 9 20 10 19 31 43 32 42 90 89 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 55 Freescale Semiconductor, Inc. 4X 0.20 (0.008) L-M N H 4X 25 TIPS 100 76 0.20 (0.008) L-M N T CASE 983-01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.350 (0.014). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.070 (0.003). 1 75 -L- -MB V 3X VIEW Y B1 25 51 V1 Freescale Semiconductor, Inc... 26 A1 S1 A S -N- 50 C -H-TSEATING PLANE 4X 2 0.08 (0.003) T 4X 3 VIEW AA S 0.05 (0.002) W 1 C2 2XR R1 C L AB G DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3 MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.10 0.30 0.45 0.75 0.15 0.23 0.50 BSC 0.07 0.20 0.50 REF 0.08 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 7 0 --12 e REF 4 13 BASE METAL F J U D 0.25 (0.010) GAGE PLANE C1 VIEW AA K E Z AB VIEW Y -XX = L, M AND N PLATING M 0.08 (0.003) T L-M S NS SECTION AB-AB ROTATED 90 CLOCKWISE Table 35. 100-pin Thin Quad Flat Pack (TQFP) Mechanical Information 56 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Ordering Drawings 4.2 Ordering Drawings Complete mechanical information regarding DSP56824 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain instructions for using this system: (602) 244-6609 The automated system requests the following information: * * The receiving fax telephone number including area code or country code The caller's Personal Identification Number (PIN) NOTE: Freescale Semiconductor, Inc... For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. -- The type of information requested: -- Instructions for using the system -- A literature order form -- Specific part technical information or data sheets -- Other information described by the system messages A total of three documents can be ordered per call. The mechanical drawings for the 100-pin TQFP package are referenced as 983-01. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 57 Freescale Semiconductor, Inc. Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: Where: TJ = T A + ( P D x R JA ) Freescale Semiconductor, Inc... TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: Where: RJA = RJC + R CA RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. * 58 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Thermal Design Considerations * Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. Freescale Semiconductor, Inc... As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization Parameter, or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. NOTE: Table 19 on page 20 contains the package thermal values for this chip. DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 59 Freescale Semiconductor, Inc. 5.2 Electrical Design Considerations WARNING: This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of considerations to assure correct DSP operation: * Freescale Semiconductor, Inc... Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place six 0.01-0.1 F capacitors positioned as close as possible to the package supply pins, one capacitor for each of the "Circuits Supplied" groups listed in Table 34 on page 55. The recommended bypass configuration is to place one bypass capacitor on each of the ten VDD/VSS pairs, including VDDPLL/VSSPLL. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are less than 0.5" per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND. Bypass the VDD and GND layers of the PCB with approximately 100 F, preferably with a highgrade capacitor such as a tantalum capacitor. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the VDDPLL and VSSPLL pins. When using Wired-OR mode on the SPI or the MODx/IRQx pins, the user must provide an external pull-up device. Designs that utilize the TRST/DE pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. Designs that do not require debugging functionality, such as consumer products, should tie these pins together. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. * * * * * * * * * * * 60 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical Design Considerations Part 6 Ordering Information Table 36 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 36. DSP56824 Ordering Information Part DSP56824 Supply Voltage 2.7-3.6 V Package Type Plastic Thin Quad Flat Pack (TQFP) Pin Count 100 Frequency (MHz) 70 Order Number DSP56824BU70 Freescale Semiconductor, Inc... DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com 61 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MFAX and OnCETM are trademarks of Motorola, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. All other tradenames, trademarks, and registered trademarks are the property of their respective owners. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan, Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, 2 Tai Po, N.T., Hong Kong. 852-26668334 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com -TOUCHTONE 1-602-244-6609 -US & Canada ONLY 1-800-774-184 -http://sps.motorola.com/mfax/ HOME PAGE: http://motorola.com/sps Motorola DSP Products Home Page: http://www.motorola-dsp.com For More Information On This Product, Go to: www.freescale.com DSP56824/D |
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